The present disclosure relates to a protection circuit which prevents electrostatic breakdown of a semiconductor integrated circuit from being caused, and a semiconductor integrated circuit including the same.
Heretofore, for the purpose of preventing electrostatic breakdown of an internal circuit from being caused, a semiconductor integrated circuit has been provided with an Electro Static Discharge (ESD) protection circuit. Also, in general, a Resistance-capacitance (RC) trigger type power clamp Metal Oxide Semiconductor (MOS) circuit is used as the ESD protection circuit. This RC trigger type power clamp MOS circuit, for example, is described in Japanese Patent Laid-Open No. 2004-14929.
This type of ESD protection circuit normally includes an RC series circuit having a resistive element and a capacitive element, and a Complementary MOS (CMOS) inverter. In this case, the RC series circuit is provided between a power source wiring and a grounding wiring. Also, an input terminal of the CMOS inverter is connected to a connection point between the resistive element and the capacitive element of the RC series circuit. In addition, the ESD protection circuit includes a clamp MOS transistor composed of an N-channel MOS Field Effect Transistor (MOSFET) in which a conductivity type of current carriers is an N type. A gate terminal of the clamp MOS transistor is connected to an output terminal of the CMOS inverter, and a drain terminal and a source terminal of the clamp MOS transistor are connected to the power source wiring and the grounding wiring, respectively.
In the ESD protection circuit having the configuration described above, the moment an ESD surge (high-voltage pulse) is generated to enter the ESD protection circuit, a through current is caused to flow through the RC series circuit of the resistive element and the capacitive element, and thus a voltage level developed at an input terminal of the CMOS inverter is changed from a High level to a Low level. As a result, a signal (voltage) set at the High level is applied from the CMOS inverter to the gate terminal of the clamp MOS transistor, so that the clamp MOS transistor is set in an ON state. As a result, an ESD surge current is caused to flow through a channel between a drain region and a source region of the clamp MOS transistor, thereby making it possible to protect an internal circuit of the semiconductor integrated circuit. It is noted that in the ESD protection circuit having the configuration described above, a period of time for which in a phase of generation of the ESD, the clamp MOS transistor becomes the ON state (a time for current flow of the ESD surge current) is determined depending on a time constant (RC) of the RC series circuit.
In addition, heretofore, there has been proposed an ESD protection circuit configured in such a way that the ESD protection circuit supplies an output signal from a CMOS inverter not only to a gate terminal of a clamp MOS transistor, but also to a well region (body). This ESD protection circuit, for example, is described in Japanese Patent Laid-Open No. 2006-121007.